1. Field of the Invention
The present invention relates to a data processing device with a test control circuit which is capable of efficiently executing a function test for an I/O device such as a Read Only Memory (ROM), Random Access Memory, and other elements incorporated in an one-chip microcomputer.
2. Description of the Prior Art
FIG. 1 is a block diagram of a single chip microcomputer 1 in which a central processing unit (CPU) 2 as a main control unit, a random access memory (RAM) 3, a read only memory (ROM) 3, and other elements are incorporated in one chip.
In the same diagram, the single chip microcomputer 1 comprises the CPU 2, and peripheral devices 3 and 4 in addition to the CPU 2 (hereinafter referred to as I/O devices) which are connected through an address bus (AB) 5 and a data bus (DB) 6, fabricated from the one semiconductor chip.
The microcomputer, for example, is connected to an external I/O device 7 to extend the functions thereof.
In this case, the external I/O device 7 is connected to the I/O device 4, which is capable of acting as an interface circuit through the address and data buses 8 and 9 in the microcomputer 1.
When test operations, function tests, trouble shooting, and analysis of faulty units for the I/O device are executed under the control of a LSI tester 10 (as shown in FIG. 2A) the device of the present invention acts as a testing system which is connected to the microcomputer 1 through a bus 9.
For example, the test operations are carried out as follows:
First, the LSI tester 10 transfers an instruction for the test operation to the CPU 2 through a path A.
Second, the CPU 2 transfers a target address to the I/O device 3 as the target device for the test operation through a path B.
Third, the contents of the I/O device 3 are read out to a register (not shown) in the CPU 2 through a path C.
Finally, the contents of the I/O device 3 stored in the register in the CPU 2 are transferred to the LSI tester 10 through a path D, as shown in FIG. 2B, or the contents of the I/O device 3 are directly read out to the LSI tester 10 when they are provided to the CPU 2 through the data bus 6, as shown in FIG. 2C.
Specifically, the readout and other operations for the I/O device 3 as the target device for the test operations are controlled by the instructions provided from the CPU 2.
The CPU 2 must execute a fetch operation to obtain the instructions and the effective address for the test operations, then access the I/O device 3 as the target device when the test operations as described above are carried out under the control of the CPU 2.
However, only the operation to access the I/O device 3 is necessary for the test operation for the I/O device 3. Therefore no fetch operation to obtain the instructions and the effective addresses for the CPU 2 are needed.
No operation time for these fetch operations is required for the test operation.
Moreover, in this case, the many test vectors for the CPU 2 should be transferred from the LSI tester 10 to execute the test operations.
When an I/O device which handles real time information is the target device for the test operation, the information before and after the readout operations of the I/O device must be transferred to the LSI tester 10 for the correct test operations.
In the testing method for I/O devices in a microcomputer in the prior art, when another readout operation for the I/O devices must be carried out immediately after execution of the readout operations, the fetch operations for the instructions and the effective addresses for the CPU, as described above, should be executed between the two readout operations, therefore the LSI tester cannot obtain the information before and after the readout operations of the I/O device.
In such a case, a plurality of test vectors are also required to execute these operations.
As described above, the test operation for the conventional microcomputer takes much time and a plurality of test vectors because an external device such as the LSI tester 10 executes the test operations for the internal I/O devices through the microcomputer.